Powering up digital integrated circuits by connecting the positive and negative terminals of a power supply to the circuit can cause multiple transient voltage waveforms to be applied to the circuit due to the mechanical nature of making the connection of the wires to the circuit. When the circuit is powered up it is often desirable for memory devices such as flip flops to be in a known state, i.e., Q=1 or Q=0, depending on the application. If the integrated circuit is powered up and then sequentially a transient is imposed by a clumsy mechanical connection of the two wires to the power supply then an undesirable signal may be sent through the digital circuitry disturbing the initial states.
This problem can be minimized through the use of filter capacitors to the supply line of the circuit. However, due to the charge time of the capacitors, this does not eliminate the problem. A large value of capacitance would provide a more stable DC level from the power supply to the integrated circuit but in many cases it is too costly to provide this additional large capacitor, or it may be impractical to allow for the time needed to charge up the large capacitor.
It is an object of the present invention to provide a power up circuit which extends the time for powering up by using an already existing capacitor, such as the timing capacitor in an oscillator.